/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off UNDRIVEN */
`include "defines.svh"
`include "axi_defines.svh"

import "DPI-C" function int data_read(
    input bit reset,
	input int raddr,
    input int pc
);

import "DPI-C" function void data_write(
    input bit reset,
	input int waddr,
    input byte wmask,
	input int wdata,
    input int pc
);

module axi_dram(
    input  logic reset,
    input  logic clk,
    input  addr_t debug_pc,

    // AXImaster <-> AXIslave
    input  logic arvalid,
    input  addr_t araddr,
    output logic arready,

    input  logic rready,
    output data_t rdata,
    output resp_t rresp,
    output logic rvalid,

    // AXImaster <-> AXIslave
    input  logic awvalid,
    input  addr_t awaddr,
    output logic awready,

    input  logic wvalid,
    input  data_t wdata,
    input  strb_t wstrb,

    output logic wready,

    input  logic bready,
    output resp_t bresp,
    output logic bvalid
);

    // outports wire
    wire   	out_1,out_2;

    LFSR #(.INITVAL( 4'b1001  ))
    u_LFSR_1(
        .clk   	( clk    ),
        .reset 	( reset  ),
        .out   	( out_1  )
    );

    LFSR #(.INITVAL( 4'b1011  ))
    u_LFSR_2(
        .clk   	( clk    ),
        .reset 	( reset  ),
        .out   	( out_2  )
    );




    logic ar_shake,aw_shake,w_shake,b_shake;
    assign ar_shake = arready & arvalid;
    assign aw_shake = awready & awvalid;
    assign w_shake = wready & wvalid;
    assign b_shake = bready & bvalid;

    // R
    always_comb begin
        if(reset) begin
            arready = `OFF;
        end else begin
            arready = `ON; // 换成LFSR()
        end
    end
    always_ff @(posedge clk) begin
        if (reset) begin
            rvalid <= `OFF;
        end else if(ar_shake) begin
            rvalid <= `ON;
        end else begin
            rvalid <= `OFF;
        end
    end
    
    // W
    always_comb begin
        if(reset) begin
            awready = `OFF;
        end else begin
            // awready = `ON; // 换成LFSR()
            awready = out_1;
        end
    end

    always_comb begin
        if(reset) begin
            wready = `OFF;
        end else begin
            // wready <= `ON;// 换成LFSR()
            wready = out_2;
        end
    end

    always_ff @(posedge clk) begin
        if(reset) begin
        end else if(w_shake & aw_shake) begin
            bvalid <= `ON;
        end else begin
            bvalid <= `OFF;
        end 
    end


    // DATA
    always_ff @(posedge clk) begin
        if(reset) begin
            rdata <= `NULL;
        end else if(ar_shake) begin // 有读请求时
            rdata <= data_read(reset,araddr,debug_pc);
            rresp <= `OKAY;
        end else begin
            rdata <= `NULL;
            rresp <= `DECERR;
        end
    end

    always_ff @(posedge clk) begin
        if(aw_shake && w_shake) begin // 有写请求时
            data_write(reset,awaddr,{4'b0,wstrb},wdata,debug_pc);
            bresp <= `OKAY;
        end else begin
            bresp <= `DECERR;
        end
    end




endmodule
